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Thin Film Transistors

Contact: Ryoichi Ishihara

Transistors and circuits equivalent to the MOSFETs using single-crystalline Si compatible with glass or a flexible plastic substrate.
The goal of the the Thin Film Transistors program is to realize transistors and circuits equivalent to the MOSFETs using single-crystalline Si despite of the restriction of the low temperature processing compatible with a glass or flexible plastic substrate. The single grain Si TFTs are promising for complex circuit integration in flat panel displays on large glass substrate, enabling for example, a sheet like computer. The results also widen the possibilities of this technology to applications that require flexible plastic substrates. It can even be applied on already processed micro-electronic circuits or devices, i.e., 3D-ICs where various block and systems can be stacked up on each other with dense vertical interconnects. Our approach is to fabricate the TFTs inside a large Si grains fabricated through excimer laser crystallization process which gives no thermal damage to the underlying structures. One of technical challenges here is how to realize location control of large Si grain by the laser crystallization process. We have developed new methods which enable the location control of grains in two dimensional by structural modification in the substrate. In this way large (up to 9 microns) crystalline silicon islands are obtained at predetermined locations, in which subsequently the transistors are formed. Field effect mobilities of n-channel TFTs of 600 cm2/Vs have successfully been obtained with a deviation of 10%. Scientific challenge here is to understand deeply the relationship between the solidification and nucleation process, the crystalline structure, the electronic properties of the silicon film and the TFT characteristics. The program focuses on realization of high performance TFTs and also circuits in close co-operation with industry. The former requires many fabrication process development brought by the deep understanding of crystal growth kinetic and device physics of the particular configuration. The latter is performed in close cooperation with the electronics design groups.

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