Yinchi Zhao

I joined the group in September 2025 from the Department of Electrical Engineering. My current research focuses on the development of next-generation Board Level Reliability (BLR)
testing methodologies, and integrates electronic system design, artificial intelligence modeling, digital twin approaches, MEMS system integration, and multi-physics simulations to
enable system-level robustness evaluation and to explore more application possibilities.

Program: MSc Microelectronics