[2022] Low-Phase-Noise VCO for Sub-10fs-Jitter PLL (SiTime)

Background

Phase-locked loops (PLL) with high spectral purity at low power consumption are in great demand for high-performance data converters, optical communication links, wireline, and wireless transceivers. New applications impose jitter values for a PLL in the range of a few tens of femtoseconds. For example, in wireless applications, the use of 256QAM in 5G radios operating at ~28GHz necessitates an integrated phase noise of −45 dB, which translates to 30-fs RMS jitter. In macro-cellular base stations and satellite communication systems, directly digitizing signals via an RF sampling analog-to-digital converter (ADC) can significantly reduce the system’s complexity, power consumption, and cost. However, this ADC presents tough PLL design issues. For example, a 10Gs/s ADC with 12-bit resolution can tolerate less than 10-fs RMS jitter.  Wireline transceivers have steadily pushed for greater speeds, reaching rates as high as 112 Gb/s through the use of PAM4 signaling. Typical PAM4 systems employ a 7-bit ADC to digitize the received signal, calling for a jitter less than 10 fs at a clock rate of 112 GHz.

A divider-less voltage-sampling PLL (VSPLL) and charge-sampling PLL (CSPLL) reduce the jitter of a PLL to its fundamental low level [1]. More specifically, the PLL loop components contribute negligible jitter, and the VCO and crystal reference dominate the jitter contribution. Moreover, due to the high-phase detection gain of a VSPLL and CSPLL, the PLL loop components consume little power, thus making the VCO the dominant power contributor (up to 80% of the total PLL power). As the crystal phase noise is fixed, the PLL jitter can only be reduced by improving the VCO phase noise and optimizing the PLL loop bandwidth. However, the PLL loop bandwidth is limited to 1/10 of the reference frequency due to the stability concerns. Hence, the design of VCO can face daunting challenges when reaching sub-10fs level of jitter. Consequently, any power reduction in an RF oscillator will greatly benefit the overall system power efficiency. For this reason, in the last decade, the analysis of phase noise and the investigation of improved circuit techniques for VCO have attracted a large interest from both academy and industry.

Low Phase Noise Oscillator at Low Power

Our current CSPLL achieves 48.6-fs RMS jitter and −77.3-dBc reference spur at an 11.2-GHz carrier frequency while consuming 5 mW [1]. This corresponds to the best-reported jitter-power FOM and reference spur performance. To push the performance further (lower jitter and better PLL FOM), it is thus beneficial to reduce the VCO phase noise by increasing its power consumption while simultaneously improving the VCO FOM.  Given the supply voltage, the phase noise in LC VCO is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too small inductors sets a lower bound on phase noise. To overcome this limit, multi-core coupled VCO can scale down the phase noise by 10 log(N), where N is the number of coupled oscillators. Another method of reducing the phase noise of a VCO is to exploit the series resonance of a tank [2]. Compared to the parallel resonance, the series resonance dramatically reduces the equivalent resistance at the resonance frequency (Q2) and thus significantly raises the tank's active power,  enabling an ultra-low phase noise with a low voltage supply. To enhance the FOM of a VCO, there are also many options available. For example, exploiting the advantages yielded by class-C operation of the core transistors, a class-C VCO shows a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank VCO for the same current consumption, showing an excellent VCO FOM of 196dB [3]. In addition, class-D and class-F structures with tail resonance could also be exploited to improve the FOM of a VCO.

Useful Information

This project is with collaboration with SiTime Corporation and This project comes with a student stipend!

Sitime Corporation develops silicon-based timing solutions. The Company manufacturers oscillators, clock generators, and embedded resonators used for ethernet switches, computing devices, graphics cards, disk drives, mobile phones, and subscriber identity module cards. Sitime serves customers worldwide. 

References:

[1] J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Low-Jitter and Low-Spur Charge-Sampling PLL," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2021.3105335.

[2] F. Pepe, A. Bevilacqua, and P. Andreani, “On the Remarkable Performance of the Series-Resonance CMOS Oscillator” in IEEE Transactions on Circuits And Systems–I, doi: 10.1109/TCSI.2017.2727283.

[3] A. Mazzanti and P. Andreani, “Class-C harmonic CMOS VCOs, with a general result on phase noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716–2729, Dec. 2008

Assignment

·      Understanding the requirements of the targeted application

·      Deriving the VCO specifications based on the system level requirements 

·      Literature review on state-of-the-art VCO topologies

·      Simulating the circuit in cadence Finding the related issues Finding novel solutions

·      Circuit design in TSMC 40-nm CMOS 

·      Layout of test chip and Post layout simulations

·      Tape-out 

·      Preparing measurement setup

·      Measurement and analyzing the measured performance of the chip

·      Writing the thesis

·      Publishing a paper

Contact

Last modified: 2022-03-11