Carbon nanotubes as vertical interconnect in 3D integrated circuits (CNT3DIC)

Interconnect delay and power consumption is one of the biggest challenges in state-of-the-art very large-scale integrated circuits (VLSI) technology. While the downscaling of transistors in general improves their performance, downscaling of the metal interconnects actually increases their resistance, and therefore delay and power consumption. For current high performance circuitry the delays attributed to bringing signals from one part of the chip to another surpasses that of the delay associated with the actual logic gates.

One of the solutions proposed in order to reduce the impact of interconnects on the VLSI performance is 3D integration. Here, multiple levels of active devices are stacked on top of each other, therefore reducing the length of the required interconnects by allowing signal routing in an additional dimension. Several different methods exist to fabricate 3D integrated circuits: one can stack wafers, dies, or layers on the same substrate. This last approach, dubbed monolithic integration, will offer the highest integration density and shortest interconnects. The main challenges that exist with this technology are the creation of multiple device layers on the same wafer, thermal management, and reliable high aspect ratio (HAR) vertical interconnects (vias).

Previously our group has demonstrated that high-performance single-grain transistors fabricated using the so-called µ-Chrozalski method could be used to fabricate 3D logic circuits, memories and photo-diodes with integrated read-out. With this, an excellent technology for the fabrication of the multiple device layers has been presented.

To solve the issues of thermal management and reliable vias we propose that carbon nanotubes (CNT) can be an attractive candidate. CNT have been shown to have excellent thermal properties, with thermal conductivities being reported as high as 3500 W/mK at room temperature. Beside that, CNT have been shown to be able to handle current densities in the order of 109 A/cm2, three orders of magnitude higher than that of Cu, and can potentially outperform Cu in terms of electrical conductivity for high density bundles. Due to their bottom-up nature of deposition CNT can be grown at high aspect ratios, with ratios as high as 10 being demonstrated. Finally, CNT vias don�t require a diffusion barrier and pose less risk for metal contamination than Cu vias.

Cross-section of a fabricated CNT test via

Project data

Researchers: Sten Vollebregt, Ryoichi Ishihara
Starting date: October 2009
Closing date: October 2013
Sponsor: Eniac JU
Partners: JEMSiP_3D
Contact: Ryoichi Ishihara