Agenda

MSc ME Thesis Presentation

• Monday, 9 December 2024
• 14:00
• Echo Hall F

Low-cost precision Vds current sensing

Abstract. Vds current sensing is a technique where the voltage over the parasitic channel resistance of a transistor is used to estimate the current through it. When integrated into smart gate driver ICs, this has the potential to improve power density, efficiency, and cost by removing the need for dedicated shunt resistors.  However, achieving high precision requires a temperature compensation method that is traditionally unsuitable for this integration. My thesis proposes an online calibration method based on small signal resistance measurement that achieves <1% current sensing error and has measurement circuitry that is in parallel to the power stage, which opens the door to integration into smart gate driver ICs.

Overview of MSc ME Thesis Presentation