Electronic Components, Technology and Materials
Department of Microelectronics

dr. V. Jovanovic

Postdoc
Electronic Components, Technology and Materials (ECTM), Department of Microelectronics

Expertise: Advanced CMOS devices and properties of VLSI interconnect

Biography

Vladimir Jovanovic was born in 1976 in Slavonski Brod, Croatia. From 1994 he studied at Faculty of Electrical Engineering and Computing of University of Zagreb where he graduated in 1999 with the thesis "HCBT Technology". He earned a Master degree in the field of electronics in 2004 with the thesis "VLSI Interconnect Characteristics"?.

From 2004 he is pursuing a PhD degree in electronics at University of Zagreb. From 1999 he is employed by Faculty of Electrical Engineering and Computing. From December 2005 to September 2007 he was a guest student at Delft University of Technology, The Netherlands, where he did the experimental work of his PhD. His research interests include advanced CMOS devices and properties of VLSI interconnect. He has published over 20 papers in scientific journals and conference proceedings.

Publications

  1. Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implications
    M. Poljak; V. Jovanovic; T. Suligoj;
    Solid-State Electronics,
    Volume 65-66, pp. 130-138, 2011. DOI 10.1016/j.sse.2011.06.039.

  2. Integration of MOSFETs with SiGe dots as stressor material
    L.K. Nanver; V. Jovanovic; C. Biasotto; J. Moers; D. Gruetzmacher; J.J. Zhang; N. Hrauda; M. Stoffel; F. Pezzoli; O.G. Schmidt; L. Miglio; H. Kosina; A. Marzegalli; G. G. Vastola. Mussler; J. Stangl; G. Bauer a;
    Solid-State Electronics,
    Volume 60, Issue 1, pp. 75-83., 2011. DOI 10.1016/j.sse.2011.01.038.

  3. X-ray Nanodiffraction on a Single SiGe Quantum Dot inside a Functioning Field-Effect Transistor
    N. Hrauda; J. Zhang; E. Wintersberger; T. Etzelstorfer; B. Mandl; J. Stangl; D. Carbone; V. Holy; V. Jovanovic; C. Biasotto; L.K. Nanver; J. Moers; D. Grutzmacher; G. Bauer;
    Nano Letters,
    Volume 11, Issue 7, pp. 2875-2880, 2011. DOI 10.1021/nl2013289.

  4. Ultra-high aspect ratio FinFET technology.
    V. Jovanovic; T. Suligoj; M. Poljak; Y. Civale; L.K. Nanver;
    Solid-state electronics,
    Volume 54, Issue 9, pp. 870-876, 2010.

  5. n-Channel MOSFETs fabricated on SiGe dots for strain-enhanced mobility.
    V. Jovanovic; C. Biasotto; L.K. Nanver; J. Moers; D. Gruetzmacher; J. Gerharz; G. Mussler; J. van der Cingel; J.J. Zhang; G. Bauer; O.G. Schmidt; L. Miglio;
    IEEE Electron Device Letters,
    Volume 31, Issue 10, pp. 1083-1085, 2010.

  6. Characterization of amorphous boron layers as diffusion barrier for pure aluminium
    Agata Sakic; Vladimir Jovanovic; Parastoo Maleki; Tom L.M. Scholtes; Silvana Milosavljevic; Lis K. Nanver;
    In MIPRO 2010 International Conference,
    Opatija, Croatia, pp. 52-55, May 2010.

  7. Al-mediated Solid-Phase Epitaxy of Silicon-On-Insulator
    Agata Sakic; Yann Civale; Lis K. Nanver; Cleber Biasotto; Vladimir Jovanovic;
    In MRS Spring Meeting Symposium A: Amorphous and Polycrystalline Thin-Film Silicon Science and Technology,
    San Francisco, Apr. 2010.

  8. Field effect transistor devices based on strained Si channels above buried 2D periodic SiGe quantum dots.
    N. Hrauda; T. Etzelstorfer; J. Strangl; D. Carbone; G. Bauer; C. Biasotto; V. Jovanovic; L.K. Nanver; J. Moers; D. Gruetzmacher;
    In Materials Research Society (MRS) spring meeting,
    San Francisco, USA, 2010.

  9. MOSFETS on self assembled SiGe dots with strain enhanced mobility.
    V. Jovanovic; C. Biasotto; L.K. Nanver; J. Moers; D. Grutzmacher; J. Gerharz; G. Mussler; J. van der Cingel; J.J. Zhang; Z. Jianjun; G. Bauer; O.G. Schmidt; L. Miglio;
    In 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010),
    Shanghai, China, pp. 926-928, 2010.
    document

  10. n-channel MOSFETs fabricated on self assembled SiGe dots for strain enhanced mobility
    Vladimir Jovanovic; Cleber Biasotto; Juergen Moers; Detlev Grutzmacher; Jianjun Zhang; Nina Hrauda; Mathieu Stoffel; Fabio Pezzoli; Oliver G. Schmidt; Leo Miglio; Hans Kosina; Anna Marzegalli; Guglielmo Vastola; Greg;
    In STW-SAFE2010 Conference Proceeding,
    Veldhoven, pp. 101-104, 2010.

  11. Analytical Models of Front- and Back-Gate Potential Distribution and Threshold Voltage for Recessed Source/Drain UTB SOI MOSFETs
    B. Svilicic; V. Jovanovic; T. Suligoj;
    Solid-state electronics,
    Volume 53, Issue 5, pp. 540-547, 2009.

  12. Improving bulk FinFET DC performance in comparison to SOI FinFET
    M. Poljak; V. Jovanovic; T. Suligoj;
    Microelectronic engineering,
    Volume 86, Issue 10, pp. 2078-2085, 2009.

  13. X-ray investigation of buried SiGe islands for devices with strain-enhanced mobility
    Hrauda; N; J.J. Zhang; Stangl; J; A. Rehman-Khan; G. Bauer; M. Stoffel; O.G. Schmist; V. Jovanovic; L.K. Nanver;
    Journal of vacuum science & technology b,
    Volume 27, Issue 2, pp. 912-918, 2009.

  14. X-ray diffraction study of the composition and strain fields in buried SiGe islands
    N. Hrauda; J.J. Zhang; M. Stoffel; J. Stangl; G. Bauer; A. Rehman-Khan; V. Holy; O.G. Schmist; V. Jovanovic; L.K. Nanver;
    European physical journal-special topics,
    Volume 167, pp. 41-46, 2009.

  15. ntegration of Laser-Annealed Junctions in a Low-Temperature High-k Metal-Gate MISFET
    C. Biasotto; V. Jovanovic; V. Gonda; J. van der Cingel; Milosavljevic; S; L.K. Nanver;
    In Proceedings of the 10th International Conference on ULtimate Integration of Silicon (ULIS 2009),
    Aachen, Germany: IEEE, pp. 181-184, 2009.

  16. Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices
    V. Jovanovic; L.K. Nanver; T. Suligoj; M. Poljak;
    In Proc. of the 39th IEEE European Solid-State Device Research Conference (ESSDERC 2009),
    Athens, Greece, pp. 241-244, 2009.
    document

  17. Downscaling of Al/Si-gate MOSFETs with Self-Aligned Laser Annealed Source/Drain Junctions
    C. Biasotto; V. Jovanovic; L.K. Nanver; J. van der Cingel;
    In Proc. of SAFE 2009,
    Veldhoven, The Netherlands, pp. 189-192, 2009.
    document

  18. FinFET Considerations for 0.18 um Technology
    V. Jovanovic; M. Poljak; T. Suligoj;
    In Proc. of 45th International Conference on Microelectronics, Devices and Materials (MIDEM 2009),
    Ljubljana, Slovenija, MIDEM Society for Microelectronics, Electronic Components and Materials, 2009.
    document

  19. Laser Annealing of Self-Aligned As+ Implants in Contact Windows for Ultrashallow Junction Formation
    C. Biasotto; V. Gonda; L.K. Nanver; J. van der Cingel; Jovanovic;
    In Proc. of 24th Symposium on Microelectronics Technology and Devices Dielectric and Semiconductor Materials, Devices, and Processing (SBMicro 2009),
    Natal, Brazil, Electrochemical Society, pp. 19-27, 2009.

  20. Compact Capacitance Model for Drain-Induced Barrier-Lowering of Vertical SONFET
    B. Svilicic; V. Jovanovic; T. Suligoj;
    In Proc. of 32nd International Convention MIPRO 2009,
    Croatian Society for Information and Communication Technology, Electronics and Microelectronics, pp. 85-88, 2009.
    document

  21. Quantum Confinement and Scaling Effects in Ultra-Thin Body Double-Gate FinFETs
    M. Poljak; V. Jovanovic; T. Suligoj;
    In Proc. of 32nd International Convention MIPRO 2009,
    pp. 95-100, 2009.

  22. Application of Laser Annealing in the EU FP6 Project D-DotFET
    L.K. Nanver; V. Jovanovic; C. Biasotto; J. van der Cingel;
    In Proc. Of 17th IEEE International Conference on Advanced Thermal Processing of Semiconductors (RTP 2009),
    pp. 1-7, 2009.
    document

  23. 1.9 nm Wide Ultra-High Aspect-Ratio Bulk-Si FinFETs
    V. Jovanovic; M. Poljak; T. Suligoj; Y. Civale; L.K. Nanver;
    In Proc. 67th IEEE Device Research Conference, DRC 2009,
    2009.

  24. Suppression of Corner Effects in Triple-Gate Bulk FINFETs
    Mirko Poljak; Vladimir Jovanovic; Tomislav Suligoj;
    In Proc. EUROCON 2009,
    St. Petersburg, Russia, 2009.

  25. Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model
    B. Svilicic; V. Jovanovic; T. Suligoj;
    Solid-State Electronics,
    Volume 52, Issue 10, pp. 1505-1511, Oct. 2008.

  26. Vertical Silicon-on-Nothing FET: Subthreshold Slope Calculation Using Compact Capacitance Model
    B. Svilicic; V. Jovanovic; T. Suligoj;
    Informacije MIDEM Journal of Microelectronics Electronic Components and Materials,
    Volume 38, Issue 1, pp. 1-4, 2008.

  27. Influence of Scaling and Source/Drain Series Resistance on the Characteristics of Ultra-Thin Body FinFETs
    A. Sakic; M. Poljak; V. Jovanovic; T. Suligoj;
    In Proceedings of the 31st International Convention MIPRO,
    Zagreb, pp. 84-89, 2008.
    document

  28. Properties of Bulk FinFET with High-eps Gate Dielectric and Metal Gate Electrode
    M. Poljak; V. Jovanovic; T. Suligoj;
    In MIPRO2008,
    2008.

  29. First sub-30nm vertical Silicon-On-Nothing MOSFET
    L. Hllt; J. Schulze; I. Eisele; T. Suligoj; V. Jovanovic; P.E. Thompson;
    In MIPRO2008,
    2008.

  30. SOI vs. Bulk FinFET: Body Doping and Corner Effects Influence on Device Characteristics
    M. Poljak; V. Jovanovic; T. Suligoj;
    In MELECON2008,
    2008.

  31. FinFET technology for wide-channel devices with ultra-thin silicon body
    V. Jovanovic; T. Suligoj; P. Biljanovic; L.K. Nanver;
    In MIPRO2008,
    pp. 79-83, May 2008.

  32. Crystallographic Silicon-Etching for Ultra-High Aspect-Ratio FinFET
    V. Jovanovic; T. Suligoj; L. K. Nanver;
    In ECS 2008,
    pp. 313-320, May 2008.

  33. SiGe growth on patterned Si(001) substrates: Surface evolution and evidence of modified island coarsening
    J.J. Zhang; M. Stoffel; A. Rastrelli; O.G. Schmidt; V. Jovanovic; L.K. Nanver;
    Applied Physics Letters,
    Volume 91, 2007.

  34. Integration of Junction FETs in Back-wafer Contacted Silicon-On-Glass Technology
    V. Jovanovic; L. Shi; G. G. Lorito Piccolo; F. Sarubbi; L. K. Nanver;
    In Proc. SAFE/STW,
    Veldhoven, The Netherlands, pp. 425-429, Nov. 2007.

  35. Vertical Silicon-on-Nothing FET: Threshold Voltage Calculation Using Compact Capacitance Model
    Boris Svili�?ic; Vladimir Jovanovic; Tomislav Suligoj;
    In Proc. ISDRS 2007,
    College Park, MD, Dec. 2007.

  36. Technological constrains of bulk FinFET structure in comparison with SOI FinFET
    Mirko Poljak; Vladimir Jovanovic; Tomislav Suligoj;
    In Proc. ISDRS 2007,
    College Park, MD, Dec. 2007.

  37. Vertical Silicon-on-Nothing FET: Capacitance-Voltage Compact Modeling
    B. Svili�?ic; V. Jovanovic; T. Suligoj;
    In MIPRO 2007 International Conference,
    Opatija, Croatia, pp. 84-88, May 2007.

  38. Sub-100 nm silicon-nitride hard-mask for high aspect-ratio silicon fins
    V. Jovanovic; S. Milosavljevic; L. K. Nanver; T. Suligoj; P. Biljanovic;
    In MIPRO 2007 International Conference,
    Opatija, Croatia, pp. 62-66, May 2007.

  39. Vertical Silicon-on-Nothing FET: Analytical Model of Subthreshold Slope
    B. Svili�?iC; V. Jovanovic; T. Suligoj;
    In MIDEM 2007 International Conference,
    Bled, Slovenia, pp. 71-74, Sep. 2007.

BibTeX support

Last updated: 16 Jun 2014

Vladimir Jovanovic

Alumnus