MSc Lesly Endrinal

Lesly is an experienced Failure Analysis Technical Leader with over 25 years of combined experience in Failure Analysis (FA), Product, Test, Yield and Reliability Engineering. She earned her Master’s Degree in Electronics and Communications Engineering from De La Salle University, where she was mentored by Prof. Willem van Driel while completing her thesis on a novel backside Focused Ion Beam (FIB) application for IC package-level analysis. Lesly also holds a Bachelor’s degree in Electronics and Communications Engineering from the University of the Philippines, specializing in Digital Signals Processing.

Lesly currently serves as the Silicon FA Technical Lead at Google LLC, where she established Google’s first advanced silicon Electrical Fault Isolation (EFI) and FA triage lab from the ground up. Her extensive professional journey includes one year of being an instructor at the University of the Philippines, five years as an FA/Reliability Engineer at Analog Devices, two years as a Test Engineer at Intel, and roles as Principal FA and later Product Engineer at NXP Semiconductors in The Netherlands. She then moved to San Diego, California, to work at Qualcomm Technologies Inc, focused on collaboratively developing innovations in FA techniques, Design for FA (DFFA) and Test (DFT), partnering with design teams, EDA and CAD tool vendors to develop specialized FA features to enable diagnostics, yield bring-up and design debug. These technical contributions have resulted in several publications (including 2 Best Paper Awards at ISTFA) and four granted patents (with 2 additional patents pending).

Lesly is committed to guiding the industry’s future direction. She recently served as Chair of the Electron Device Failure Analysis Society (EDFAS) Die Level Roadmap Council (2021-2025), facilitating a global team of experts to address strategic challenges in next-generation technology. She is also a contributor to the 2025 Semiconductor Research Corporation Microelectronics and Advanced Package Technology Roadmap (SRC MAPT) 2.0 and has shared her findings at key forums including the CHIPS Metrology Workshop and Advanced Packaging Summit. Her extensive experience in technical enablement and collaboration provides a practical foundation for her doctoral research.

Last updated: 21 Oct 2025